Solving the DRAM Scaling Challenge: Rethinking the Interface between Circuits, Architecture, and Systems

Location: CS 2311 (Wireless Seminar Room)

Date & Time: Friday, April 24, 2:30 PM

Abstract: Increasing number of cores and wide adoption of in-memory applications demand high capacity main memory. Technology scaling of DRAM cells has enabled higher capacity memory for the last few decades. Unfortunately, DRAM cells become vulnerable to failure as they scale down to smaller size. Enabling higher capacity memory systems without sacrificing the reliability is a major research challenge. My work focuses on designing a scalable memory system by rethinking  the traditional assumptions in abstraction and separation of responsibilities  in two interfaces: (i) circuits and architecture, and (ii) architecture and operating systems.

Traditionally, circuit-level optimizations have ensured reliable DRAM operation. In my work, I enable DRAM scaling without the need for strict reliability guarantees from the manufacturers. I envision manufacturers shipping DRAMs without fully ensuring correct operation, and the system being responsible for detecting and mitigating DRAM failures while operating in the field. However, designing such a system is difficult due to intermittent DRAM failures. In this talk, I will present the challenges of building such a system, show the effectiveness of system-level detection and mitigation techniques, and design an intelligent system capable of providing reliability guarantees even in the presence of intermittent failures.

Leveraging the new highly scalable non-volatile memory technologies is an alternate way to enable high capacity memory. At the end of the talk, I will briefly present my recent work on rethinking the conventional memory and storage hierarchy to take advantage of the non-volatility of these technologies. I will present my vision to redefine the hardware and operating system interface to unify memory and storage system under a single address space and discuss the opportunities and challenges of such a system.

Bio: Samira Khan is a Post-Doctoral Researcher at Carnegie Mellon University, supported by Memory Research Lab at Intel and NSF GOALI Award. She is advised by Onur Mutlu. Her research focuses on improving the performance, efficiency, and reliability of the memory system. She received her PhD from the University of Texas at San Antonio. During her graduate studies, she worked at Intel Labs, AMD, and EPFL.